Adaptive Error-tolerance Scheme Based On Erasure Code Within SSDs And Its Performance Optimization

With the shrinking process size of flash memory and the development of multi-bit storage technology in cells,the capacity of NAND flash chips increases gradually,but the reliability of flash memory becomes worse.Existing reliability schemes(such as ECC and RAID)in Solid State Driver(SSD)can not deal well with the multi-level reliability problem of flash memory;in addition,the fixed reliability scheme does not consider the imbalance of wear degrees between blocks: too much redundancy is provided in the early stage of SSDs,thereby increasing the write amplification of the flash memory,and multiple errors in the stripe cannot be tolerated in the later stage of SSDs.In response to the above problems,this thesis presents an adaptive error-tolerant erasure coding scheme within SSDs,namely AetEC.In the early stage of SSDs,AetEC monitors the wear of the flash memory blocks in real time and applies RS(Reed Solomon)erasure codes with corresponding error correction capabilities,according to the number of high-wear blocks in the superblock.Then in the later stage of SSDs,the RS code's error tolerance is further increased to tolerate chip-level failures.The physical address-based stripe organization scheme effectively reduces the updating overhead of the parity data.The write cache scheme based on the double-link list partition management improves the performance of SSDs while ensuring the consistency of user data and check data.Different data recovery methods and data reconstruction layout methods are designed to deal with different types of errors.In addition,considering that the RS code implemented by the software may affect the performance of the SSD,we propose a FPGA-based multi-rate RS codec scheme.This scheme preprocesses the decoding matrix of multiple RS codes to omit the decoding matrix solution process,and uses the idea of Base-plus-Index Addressing to optimize the calculation process of the decoding matrix index,so that the throughput of decoding is almost the same as the encoding.The multi-rate RS codec is designed and implemented using Vivado HLS tools.The test results show that,the encoding and decoding have the same throughput rate: the maximum is 3GB/s;Compared with the RS decoding acceleration scheme provided by Xilinx,the multirate RS decoder achieves the same decoding rate and reduces the memory usage by 18.7%.We implement AetEC on the simulation platform and propose the reliability model of AetEC.Simulation results show that,compared with the fixed RAID4 scheme,AetEC has greater improvements in performance and reliability,and effectively reduces the write amplification of flash memory,that is,the request average response time is reduced by up to 32.8%,and the write amplification is reduced by up to 37.8%.Compared with the latest WARD scheme,AetEC achieves higher reliability with a lower performance overhead(the request average response time is increased by up to 5.9%),that is,AetEC reduces the uncorrectable page error rate(UPER)by two orders of magnitude,and provides the ability to tolerate the failure of chips.