The Verification Of Testchip For PCIE3.0PHY Based On UVM

With the continuous improvement of digital integrated circuit technology,the complexity of digital system design has increased,and the requirements for digital verification have become higher and higher.The use of efficient verification methods has become particularly important for the design of the entire chip important.Compared to traditional verification methods,UVM integrates features such as object-oriented programming,dynamic threads,and inter-thread communication,all of which allow UVM to improve design modeling capabilities at a higher level of abstraction.Designers can integrate the entire system on a single chip,and more and more products use the SOC design method.This greatly reduces the design and manufacturing costs,but the verification is more and more complicated,the cost and time required for investment More and more.The competition in the market requires the assurance of product quality while reducing the development cycle of chips.Traditional SOC verification methods do not have these conditions in many cases.Therefore,VIP verification technology has been developed.VIP components are built-in verification structures that are pre-verified by third-party manufacturers.It is easily inserted into simulation-based verification,which can greatly improve the reusability and verification efficiency of verification.At the same time,it is a verification model and a complete test environment to help design and verification engineers confirm the correctness of their design functions.VIP components are based on standard protocols,such as AMBA,PCIE,USB.The use of VIP verification technology can significantly improve the efficiency of designers and verifiers,and greatly reduce the time to create verification components and verification platforms.VIP based on systemverilog language makes it easy for verification personnel to create test scenarios and test incentives for the required verification design at the same time,the sufficiency of verification is largely ensured.This article first introduces the development process of the verification language and methodology,the characteristics of the UVM methodology and the general verification framework,analyzes and explains various mechanisms commonly used in methodology,and then introduces the layered structure of PCIE,including the transaction layer,Data link layer and physical layer,focusing on the physical layer structure and PIPE protocol,and analyzed the function of PHY.The following content is based on the verification of the PCIE3.0 physical layer test chip based on the UVM methodology.The first is the verification of the peripheral circuit of the test chip,that is,the development of the SPI interface general verification component for register configuration and the CR parallel interface verification component,Mainly including commonly used verification component driver,monitor monitor,predictor predictor,scoreboard scoreboard and the use of UVM hierarchical sequence,through the understanding of methodologies constitute an automatic comparison,configurability,coverage-driven verification The platform achieves 100% code coverage and 100% functional coverage.The second is to use VIP to verify the physical layer PHY.After analyzing and studying the functional model provided by VIP,using the common components and rich incentive models in VIP,you can quickly create a verification environment and quickly construct test cases based on this environment..By using the combination of UVM flexible mechanism and VIP,the verification platform of the test chip is more efficient and the verification results are more reliable.