Analysis And Verification Of TD-LTE Terminal Baseband Chip Physical Control Layer System

LTE(Long Term Evolution), one of the major G4 mobile communication technologies, relies mainly on orthogonal frequency division multiplexing, multiple inputs and outputs, and other key techniques to improve the system performance. The study reported in this paper improves on LTE by using carrier wave aggregate technology, which in addition to being fully compatible with 3GPP LTE, greatly enhances the peak data transmission rate and other indices of the wireless communication system. At a frequency spectrum bandwidth of 20 MHz, the peak rate is up to 600 Mbps and the peak upstream rate is up to 300 Mbps.This paper, while being set in the context of TD-LTE and based on baseband chip R&D, has its emphasis placed on the application of the physical layer control system in the baseband chip system. This paper presents the study from three major aspects.Firstly, the theoretical part of the physical layer is described, followed by an analysis of key LTE technologies, the physical layer frame structure, the data processing procedure, and the control procedure, and additionally the physical layer link is modeled and mapped to the baseband chip system to enable normal operation of the physical layer algorithm link in the baseband chip system. Next, a description is given of the physical control system, a detailed account is given of the master control module OpenRISC1200, on-chip bus, and main control module, and critical strategies for controlling the physical layer, such as interrupt control strategy, interaction control strategy, and data control strategy, are designed; a debuggable interface is developed and devised, which provides a solid support in verifying the system functions. Finally,this paper analyzes the hardware environment realized on the baseband chip by the physical layer control system, describes the implementation of the software architecture, and investigates the roles played by the control system in baseband chip function verification; the paper also describes module-level and system-level VCSfront-end simulation verification, in the process of which the chips after tape-out receive FPGA prototype verification.