A Low Power Design Of Data Plane Module In 5G Baseband

5G baseband shares the characteristics of large flow,high peak and low delay,and is widely used in AI,Internet of things and other fields.In 5G baseband So C system design,it is an important part to get the balance of performance,area and power consumption.In So C design,a large number of IP modules are often used to reduce the design workload,but this will introduce additional power consumption overhead,and the reduction of process process will introduce more static power leakage,which leaves optimization space for low-power design.With the wide application of 5G baseband in mobile terminals,the high power consumption of 5G baseband chips will seriously affect the use of mobile phones,so the low power consumption design requirements of baseband chips will also increase.The optimal design of low power in 5G baseband chip design has become a crucial step.In order to process the huge data traffic,5G baseband introduces the idea of traditional network transmission processing chip in the design,at the same time,it adds a new data plane module,and introduces a variety of protocol accelerator units in the module to realize the function of protocol L2 / L3.Data plane module is the largest module,accounting for 12% after removing 55% of the occupied area of 5g NR L1 physical layer;it is also the largest module in the control processing module of 5g baseband chip,including the module with the largest number of processing cores.In this paper,the low-power design is specifically optimized for the data plane module under the 14 nm process,based on the activities during the upstream and downstream of 5G in specific scenarios.It mainly uses DVFS design to optimize the low-power design of the system level data plane module,uses power gating and clock gating technology to optimize the internal sub units of LX7 in the data plane module LX7 subsystem,uses dynamic clock gating technology and memory maintenance function to optimize the low-power memory of the data plane module,and uses deep sleep mode to optimize the data The CR8 subsystem of plane module is optimized for low power consumption.According to the above low-power design points,use simulation tools Verdi and VCS to verify the function points,and use UPF tools and power artist tools to simulate test cases.The experimental results show that the low-power optimal design scheme proposed in this paper can reduce the power consumption of the data plane module by 20% in idle state and by 31% in normal working condition,and greatly improve the power consumption of the module under the condition of paying little extra area overhead,making the baseband chip have less heat and lower packaging cost.This paper provides a new design idea for low-power design of 5G baseband,which is conducive to the improvement and development of 5G baseband chip design.