Design And Implementation Of FPGA-based LDPC Codec For Laser Communications Between Satellites

Since the 1980s and 1990s,the Consultative Committee for Space Data System(CCSDS)has successively formulated and released a series of protocol specifications and standards for satellite communications.They specified the code type and code rate of Turbo codes and low density parity check(LDPC)codes in channel coding.They have been applied on satellite communications for many years.LDPC codes,with their excellent performance and wide application in satellite digital broadcasting,have gradually been applied in high-speed communication system between satellite and ground.We have recognized the possibility that LDPC codes as an channel coding scheme may be popular in FSO communications.In recent years FSO have attracted a lot attention in the research of wireless communications.FSO communications refer to the replacement of the original optical fiber transmission by wireless laser,which has the advantage of far transmission distance compared with optical fiber communications.Compared with traditional radio frequency(RF)communications,FSO communications allow a huge increase in available bandwidth and data rate.In this paper,we took the wireless laser communications between satellites as the application scenario and studied the application of LDPC codes in wireless laser communications.We optimized the algorithm of coding and decoding for LDPC codes to improve the throughput of codec with File-Programmable Gate Array(FPGA).We compared the implementation complexity of some algorithms based on Belief-Propagation(BP).They are sum-product algorithm(SPA),layered decoding algorithm,minimum-sum algorithm(MSA),normalization MSA(NMSA)and offset MSA(OMSA).Finally,LDA based on NMSA which has a faster convergence rate and a code gain approach SPA is implemented with hardware.Some performance curves are shown to compare the parameters of LDA.Problems in implementation of codec and the solutions are introduced in detail.Details of logic structures and functions of modules in codec are also shown with cost of resource after synthesizing and implementing using Vivado design suits.A xc7vx690tffg1927-2L FPGA chip produced in Xilinx has been applied on simulation experiment.The result of experiment after synthesize and implement in Vivado shows the coder can normally work with 400 MHz.The highest throughput of coder can approach approximately 48 Gbps.In design of LDPC decoder,a scheme called inter-frame pipeline which could raise the throughput by storing a few frames of external information.The decoder can work with 400 MHz and the throughput of a decoder can approach 4 Gbps.A FPGA chip can approach approximately 20 Gbps after five cores of decoder have been put on the chip.