Research And Hardware Implementation Of Layered ADMM Decoding Algorithm For LDPC Codes

In communication system models,channel coding techniques ensure the reliability of information transmission.Low Density Parity Check(LDPC)coding technology is simple and has performance close to the Shannon limit,making it widely used in modern communication coding fields.Belief Propagation(BP)decoding algorithm and Alternating Direction Method of Multipliers(ADMM)decoding algorithm are two commonly used decoding algorithms for LDPC codes.BP decoding algorithm has excellent decoding performance at low signal-to-noise ratios,and it has low algorithm complexity,making it widely researched and applied.However,BP decoding algorithm has an error floor at high signal-to-noise ratios,and decoding performance sharply declines.ADMM decoding algorithm has no error floor at high signal-to-noise ratios and has Maximum Likelihood guarantee,making it of great research value.The parity check polytope projection is the most complex part of the ADMM decoding algorithm.Many research scholars have conducted in-depth studies on it,proposing Cut Search Algorithm,Line Segment Projection Algorithm,and the latest Triangle Projection Algorithm proposed by our laboratory.In the scheduling mode of the decoding algorithm,layered scheduling can accelerate the convergence speed of the decoding,reduce the number of iterations,and improve the efficiency of the decoder.The key to applying decoding algorithms to practical applications lies in hardware implementation.This thesis conducts hardware implementation research based on the Triangle Projection Algorithm and layered ADMM decoding algorithm,and carries out the following work:1、Based on the Triangle Projection Algorithm,algorithm optimization was carried out to eliminate algorithm branches,merge intermediate variables,perform central symmetrization,and perform fixed-point quantization of floating-point data.Hardware design and implementation were performed for the Triangle Projection Algorithm.The TPA hardware module implemented in this thesis has performance consistent with the accurate projection algorithm CSA,with an increase in decoding efficiency of 58.5%,the LUT resources and FF resources have decreased by 39.8% and 81.7% respectively,and a50% reduction in DSP resource consumption.2、In order to optimize the hardware implementation of the layered ADMM decoding algorithm,the layered ADMM-TPA hardware decoder was designed and implemented,and detailed introductions and functional simulation tests were conducted for each module of the decoder.A complete hardware decoder was built on a Field Programmable Logic Gate Array(FPGA)platform.The layered ADMM-TPA hardware decoder implemented in this thesis can decode correctly and was successfully verified on the board.The number of iterations is reduced by about 40% compared to the Flooding ADMM-TPA hardware decoder,and the decoding efficiency is improved by about 18%.The layered ADMM-TPA hardware decoder in this article improves decoding efficiency by about 13% compared to the ADMM-CSA hardware decoder.