Research On Verification Method Of CAN Bus Controller Based On UVM

The complexity of So C design is increasing,and the time required for the chip to be put into the market is getting longer and longer,while the market needs the chip to be put into the market as soon as possible.The contradiction between the two is becoming more and more serious.Nowadays,the functional verification of the chip has become a serious challenge for IC design.Using traditional verification methods,it is impossible to traverse all possible situations,and there will be some unforeseen vulnerabilities.To solve this problem,as a new verification scheme,UVM verification platform has the functions of generating random constrained incentives,automatically collecting coverage,analyzing verification results and being reusable.Compared with the traditional verification scheme,it has obvious randomness verification and efficiency improvement,can effectively find design problems,shorten the chip production cycle.In this thesis,the CAN bus controller verification is taken as the research background.Based on the UVM verification methodology,the verification of the research object is completed by System Verilog language.The specific research results of this paper are as follows:The decomposition of the verification point of the circuit to be tested is completed.The circuit to be tested includes two working states of standard mode and extended mode.Based on direct verification thinking,according to its bus architecture,register parameter configuration,working principle and message transmission process,based on the decomposition of the verification point is completed based on the CAN2.0 protocol.In this paper,according to two different modes,the verification points are mainly decomposed into the functions of transmission and reception,transmission and reception interrupt,data overflow,arbitration capture,error detection,register reset value and read/write verification,sampling multiple times and status verification.The UVM verification platform was developed.Based on the decomposition of the verification point,the UVM verification platform is first designed,including the design and implementation of components such as monitors,drivers,scoreboards,reference models,etc.,and the sequence is applied.Mechanisms,phases mechanism,factory mechanism andother mechanisms to ensure the reusability of the UVM verification platform,and finally build a UVM verification platform with random constraint excitation and functional coverage collection,and write test cases based on the decomposed verification function points.Through the test case startup platform to simulate,the module level verification of the CAN bus controller is completed,so that the design function to be verified runs normally and conforms to the design specification.Analyze the completeness of the verification process,including collection of functional coverage and collection of code coverage and tracking of defect rates.In this paper,the information coverage of functional coverage is collected through the design of the overlay group,and the code coverage is collected through simulation software.Among them,the function coverage rate reaches 100%,the overall code coverage rate reaches 95.41%(block coverage rate is 94.38%,expression coverage rate is 94.54%,state machine coverage rate is 98.24%),and both coverage rates meet the specified verification index requirements.Achieved the purpose and value of verification.The defect rate tracking in this paper mainly completes the analysis of the defect rate curve and the analysis of the defect types through statistical tools.The analysis results show that the defect rate curve of the project shows a decreasing convergence state,and the types of defects found are the transformation trend from basic defects to advanced defects,which meets the quality requirements of verification.This thesis completed the construction of the UVM verification platform of the CAN bus controller.At the same time,the module was verified by directional test and random test.The log file and circuit simulation waveform were simulated and analyzed by NCSim and other software,and the DUT circuit was completed with high efficiency.Verification,overall,makes the chip's verification efficiency higher and the overall chip development cycle shortened.