Inter/intra-chip optical network design for manycore processors

Manycore processor system is becoming an attractive platform for applications seeking both high performance and high energy efficiency. However, huge communication demands among cores and the high power density are two significant limitations for the scalability of the single processor chip. At the same time, the potential of interconnecting multiple chips to form a large manycore processor system is also heavily confined by the limited off-chip bandwidth. In this thesis, I propose optical networks, which are based on emerging silicon photonic technologies, to effectively address both the intra-chip and inter-chip communication requirements, and thus improve the system scalability. An inter/intra-chip optical network is composed of multiple intra-chip networks each for a chip, and an inter-chip network seamlessly interconnecting them. The inter-chip and intra-chip networks are carefully coordinated with each other to balance the traffics and reduce the network resources at the interfaces. Different topologies including fat-tree and ring have been studied for intra-chip network, and corresponding inter-chip networks have been designed to address the inter-chip communication. By exploring the inherent properties of optical links and devices, I have proposed new communication fabrics design and control mechanisms for the optical networks. The data channel is designed to support bidirectional transmission and multiple concurrent transactions to boost the throughput and reduce the power consumption. The logically-distributed but physically-centralized control scheme, based on optical transfer of control signals, has been proposed to improve the arbitration efficiency and the resource utilization. I have developed cycle-accurate simulators with detailed power models to compare proposed designs with related works, and the results show that the proposed networks have achieved high performance with a small power budget.