Many-core Processor Design Based On Hybrid Interconnect Architecture

With the development of integrated circuits,more and more processing cores can be integrated on a single chip.Multicore systems have higher energy efficiency and computational performance than single cores,but data copies from different cores can cause Cache consistency issues.As the number of cores grows,the system structure changes from multi-core to many-core,and the hardware overhead and network traffic required to maintain consistency grow rapidly.At the same time,since the data interaction of the core nodes in most applications is non-global,while the nodes of the conventiornal on-chip network are globally accessible,the core network design of the many cores is also redundant.Aiming at the characteristics of non-global interaction of nodes in most applications,the paper implements a low-power multi-core processor with independent horizontal and vertical data sharing.The system mainly adopts a data sharing scheme,and sets a partitioned arrangement and a global shared data cache structure.Each node core of the system includes a unified external interface,and data caches between cores can access each other.For the node non-global interactive application,the on-chip network structure differentiated by the horizontal and vertical channels and the local interconnect structure for accelerating the data interaction between the adjacent nodes are also designed.At the same time,because multiple cores in the core structure will cause high heat generation at the same time,a low-power solution based on Power Gating shutdown technology is added to the design,so that each node core of the system can work flexibly in sleep mode.Lite mode and high performance mode.First,the hardware implementation of the design is performed using the System Verilog language.Then,the system and each module are functionally simulated using the Verilog Compile Simulator tool,and then synthesized by the Design Compiler tool.Finally,the power analysis is performed using the Prime Time PX tool.Because the system adopts the data global sharing scheme,the structure of the directory that maintains the cache consistency is omitted,and the data cache part of the design can save the hardware overhead of 10.96%to 34.686%.The many-core processor has a performance improvement of 29.157 times compared to a single core at 8*8 scale.In addition,because the system incorporates a low-power design,the node core can reduce power consumption by 40.384%in the lean mode,and consume almost no power in the sleep mode.The power consumption of the entire system will also account for the simple operation in the application.The increase is reduced.