| As advances in semiconductor technology allow for the creation of digital circuits and systems of ever increasing speed, the synchronous techniques of VLSI, or integrated system, design become correspondingly more difficult to apply. The crux of the problem rests with the distribution and synchronization of very high speed clock signals over large area, high density dies. With the emergence of gallium arsenide as a viable digital technology occurring in parallel with the constant advances in the speed and complexity available from silicon processes, diffusion delays along physically long signal lines could conceivably become comparable to propagation delays through logic elements. Effecting global synchronization under these conditions is difficult at best, impossible at worst.; A well known technique for the elimination of clock signals from digital systems is the use of self-timed signaling. In a self-timed system, particularly those operating in the environment described above, elements communicate and synchronize through a well defined protocol involving the three logical values 0, 1 and undefined. Historically, the encoding of these three logical values has been accomplished using a binary, double-rail code, incurring significant cost in logical and physical complexity, as well as in interconnection, requiring two wires per datum.; We propose a more direct implementation of self-timed systems in which the three logic levels are encoded electrically, allowing single-wire data communication between self-timed elements. In this organization, both data processing and communication functions are accomplished via ternary, rather than binary, logic elements. Interconnection complexity remains roughly equivalent to synchronous binary systems and, with careful design, logical complexity can be made comparable to self-timed, binary double-rail systems.; Toward that end, a ternary algebra has been developed from which self-timed systems can be logically specified and constructed. This mathematical tool allows the use of the binary techniques of logic design to be utilized in the synthesis of ternary logic functions. Further, because the algebra and logical structure are general in nature, the methodology is applicable to any technology; only the specific ternary circuits need be had. Finally, as the aspirant application of the ideas in this work is in high speed, VLSI, implementations, the concept is demonstrated experimentally through the parallel development of complete self-timed systems in silicon MOS and ternary logic circuits in GaAs. |
