A novel low power multi path double precision fused multiplier accumulator architecture

The floating-point fused multiply-add unit has several advantages in a floating-point unit design. This thesis presents the results of the research, design and implementation of a novel architecture for low power double precision floating-point fused multiply-accumulate (FPMAC) unit. This architecture has been designed to provide a simple solution to the high power consumption and high latency found in modern-day fused multiply-add units. The proposed architecture improves the latency of the operation by removing the dependency between operations, thereby adding more parallel operations with minimum hardware overhead. The proposed fused multiplier accumulator architecture reduces the interconnection between components which was found to be dominant among most FPMAC designs. The basic logic blocks, which are part of the multiplier accumulator architecture are individually analyzed and optimized for power and latency. The proposed architecture showed a significant reduction in power and latency when analyzed using the TSMC 180nm process library.