| The biggest advantage of implementing any design in VLSI would be a compact and simple architecture and minimum delay results. The 16 bit serial parallel multiplier architecture proposed by B. Al Besher, A. Bouridane, A. S. Ashur and D.Crookes [1] has been designed with a simple yet effective layout design in MAGIC and been simulated in HSPICE for power and delay results. The multiplier proposed uses the redundant number system format and multiplier is fed serially whereas the multiplicand is fed in parallel. Since parallel multiplier is hard to implement onto single chip hardware, a serial parallel multiplier is used. The entire design is implemented in TSMC 0.35um technology for optimum results. |
