Architectures and circuit techniques for adaptive equalizers and numerically controlled oscillators in digital modem applications

High-speed circuit techniques and optimized architectures for several computation-intensive building blocks in an all-digital Quadrature-Amplitude-Modulation (QAM) communication system have been developed. The design concepts have been validated by realizing these building blocks as CMOS Integrated Circuits (IC's). A Numerically Controlled Oscillator (NCO), a Decision-Feedback Equalizer (DFE), and a Feed-Forward linear transversal Equalizer (FFE) have been developed, and their tested performance exceeds all previously reported comparable IC's.;In standard CMOS processes; pseudo-NMOS logic is sometimes used to achieve high speeds in non-pipelined circuits. However, pseudo-NMOS consumes large amounts of power and its performance is sensitive to IC process variations. To solve both problems, a new circuit design technique called Adaptively-Biased Pseudo-NMOS Logic (APNL) has been proposed. The layout and simulations show that a differential APNL full-adder cell is nearly 80% faster than conventional Cascode Voltage Switch Logic (CVSL) and over 30% faster than the Domino CVSL circuits, while consuming comparable power and silicon area. This and other high-speed circuit techniques have been applied to the IC's introduced in this dissertation.;To accomplish timing recovery/synthesis in modem systems, a 24-bit NCO chip using a circuit design technique called True Single-Phase Clock (TSPC) pipelined CMOS has been designed and fabricated in a standard IC process. The maximum input clock rate of 700 MHz well exceeds all existing CMOS phase accumulators, and matches the speeds of similar ECL and GaAs devices but requires much less power consumption.;To perform high-throughput QAM channel equalization, a 60-MBaud DFE/FFE chip set was designed and tested which can handle signal formats from QPSK up to 256-QAM. The FFE is configurable into either a symbol-spaced or fractionally-spaced equalizer. The proposed APNL circuit technique was adopted to reduce the DFE critical-path delay. The coefficient updating circuitry for implementing the LMS algorithm is included on both chips with programmable adaptation step sizes. By using the cut-set re-timing technique, both chips are fully cascadable to implement higher-order adaptive filters without any speed degradation. The optimized parallel architecture of the chip set results in a computation power over an order of magnitude higher than achievable with general-purpose Digital Signal Processor (DSP) chips.