| This thesis begins with the discussion of the background and motivation of this thesis, CMOS technology and circuit logic, and then low-power high-speed circuit techniques and design bottlenecks are reviewed.;Based on the comprehensive overview, a number of advanced design strategies and key circuit techniques such as DC bias optimizing, device sizing, split-resister (S-R) low capacitive load, compact active inductor, MOS-based capacitor and resistor, active negative feedback topology are identified and analyzed to realize low-power high-speed circuits with reduced silicon area.;To validate the selected strategies and techniques, a low-jitter wide tuning range CDR, three low-power 1.25-Gb/s to 10-Gb/s limiting amplifiers, a high modulation efficiency LDD/MD were designed and fabricated; 1V-supply circuits such as 1:2 DE-MUX, 2:1 MUX, data decision circuit, and high input sensitivity 2:1 static frequency divider were designed and simulated.;Finally, the measurement data and post-layout simulation data confirmed that the selected circuit techniques and design strategies indeed results in circuits with lower power dissipation or lower supply voltage, and higher operating speed. |
