| It is proposed to create a test bed to ease algorithm and hardware development tasks. The advances in VLSI have created a situation in which complex signal processing algorithms are considered even for high speed, high computational complexity applications (HDSL, speech processing, and mobile communications can serve as examples). For these applications for which only an incomplete analytical performance evaluation can be made, the problem of signal processing algorithm verification becomes a bottleneck in both research and hardware development stages. A programmable hardware algorithm evaluation system capable of operating at or near real-time for the data rates of interest is required. A multiprocessor system based on a slotted ring bus communication scheme has been adopted as a compromise between interconnection bus complexity and bus transfer efficiency. Review of selected DSP system algorithms has been used to verify the design choices. Then the hardware was implemented based on the TMS320C30, tested, and benchmark results given. The test bed discussed here can serve as a test bed for complex (digital) signal processing algorithms. The speed up in evaluation time creates, for the user, nearly "a final product" testing situation providing results at or near real time. |
