Virtual hardware based ATM switching node test system

As Asynchronous Transfer Mode (ATM) emerges as the best technology for suitably integrating the various traffic classes of present and future broadband integrated services digital networks, testing methods and equipments associated with this technology have to be devised. The high bandwidth of ATM as well as its flexibility in terms of supported traffic types prevent the use of conventional approaches to network technology testing. Particularly, the conformance assessment of ATM switching nodes becomes a very challenging task because of their complex functionality and the sophisticated performance issues involved. This thesis presents a design and implementation of an ATM switching node test system based on static RAM type Field-Programmable Gate Array (FPGA) technology. Real-time reprogrammability of the FPGA technology used results in a high functionality virtual hardware system requiring very few hardware components. The test system features the high performance Synchronous Optical Network (SONET) and Synchronous Digital Hierarchy (SDH) fibre protocols as the physical link for the connection to the switching nodes under test.