| The objective of this thesis is to present the architecture and peripheral circuits suitable for the implementation of a 5V only ZE 2PROM memory. First, the development of a large signal model of the cell for circuit simulations is presented. The proposed model is implemented as a subcircuit in the HSPICE simulator.; A novel "Shared Bit Line, Alternating Word Line" architecture is proposed to achieve high density for the memory. The peripheral circuits that can implement the read, program and erase modes of operations in this architecture are presented. High voltage issues in a low voltage process are addressed. The implementation of the positive and negative charge pump circuits that generate the required programming and erasing voltages using a 5V power supply are presented. |
