The Research On Power Optimization Of Technology-dependent Combination Circuits Based On Static Logic Implications

With the development of CMOS and the increasing use of portable communication products, power dissipation is becoming a critical problem. Since much work has been done on power optimization techniques at all stage of the design process, this paper mainly study on how to reduce the power dissipation in logic stage of circuit design.This paper presents a method to the problem of optimizing technology mapped combinational circuits for low power. After each node's switching activity in the circuit is determined, high-power nodes are eliminated through redundancy addition and removal. To do so, the nodes are sorted according to their switching activity, they are considered one at a time, and recursive learning is used to identify logic implications inside the network. These logic implications are exploited to add gates and connections to the circuit to increase redundancy for removal later; this may help in eliminating high-power dissipating nodes, thus reducing the power dissipation of the entire circuit. The process is iterative; each iteration starts with a different target node. The end result is a circuit with a decreased switching power without changing the input-output function. Experimental results show the effectiveness of the proposed technique.During the above process, power optimization greatly depends on the number of logic implication found in circuits. Although Recursive learning is a complete method to find logic implication given enough time, in practical the depth of recursion must be restricted to keep the execution time within reasonable bounds considering the NP-hard of looking for all logic implication in circuits. Therefore, an improved logic implication algorithm has been proposed, which was inspired by the by the single pass deductive fault simulation algorithm. It fully takes advantage of the special context of static implication and set algebra to introduce a series of basic laws, which form the core of the new algorithm. It is iterative, unlike the recursive method mentioned above.Under SIS, this paper realizes this improved logic implication algorithm. Using this algorithm, we perform logic implication searching on several typical circuits from the Mcnc'91 benchmark suite. The experimental results show that the new algorithm can find more general implication during reasonable time. Therefore, this enhancement should allow us to reduce power dissipation further.