| This thesis focuses on the hardware implementation of parallel concatenated coding schemes (Turbo Codes) for varying applications. The goal of this research is to prove the usefulness of Turbo Coding implementations for applications such as cellular, where real-time high bandwidth processing is required, as well as for post-processing of data for signals transmitted in low SNR environments, which do not require real-time processing, but require more memory resources. The results of the hardware implementation of a Turbo Decoding algorithm on the TI TMS320 digital signal processor are presented. Though the hardware implementation is on a fixed point DSP architecture, the issues that are discussed are applicable to other processing architectures such as FPGA, CPLD, and ASIC. Benchmarks for evaluating the performance of hardware implementations are featured, as well as solutions for practical issues such as generating test data, loading the data onto the hardware, and post-processing the hardware output for verification. |
