Hardware/Software Co-Design And Implementation Of Video Coding System

Real-time video processing is widely used in areas such as live streaming, video communication and so on. Video compression is an important step in video processing and balances the conflict between video compress rate and video quality. With the advance in video compression technology, fewer bits are needed to compress a video under the same video quaility. However, increased computational complexity makes it difficult to meet the real-time requirement for video compression running in software. Schemes based on ASIC, DSP, FPGA are proposed.The rapid progress of FPGA technology in integration, low power consumption and parallel execution provides a high performance platform for hardware/software codesign implememtations. Two major FPGA vendors, Xilinx and Altera, introduced ARM based So C FPGA chips successively. This kind of chips integrate ARM processors and programmable logic fibers. ARM-FPGA chips have all advantages of FPGA in digital image processing and make full use of peripheral devices by using ARM processor.This paper implements a video coding system based on DE1 So C FPGA platform power by Altera Cyclone V So C in which funtional IP cores are created and controlled by ARM. Performance improvements of the system is the result of the advance in integrated circuit technique and electrical system.This paper tests the coding efficiency of free encoder on ARM Cortex-A9@800MHz and gives a HW/SW partition scheme cosidering test results and complexity of implementation. After analyzing the structure of the H.264 encoder, the basic principles of modules in H.264 intra coding loop is studied and an intra encoder is implemented, which includes a luma 4x4 intra prediction module with 3 predict modes, a chroma 8x8 intra prediction module with 3 predict modes, a 4x4 transform module, a 2x2 hardmard transform module, and a quantizer.Video capture, encoding and preview are implemented on FPGA side. Control logic and sending functions are finished on ARM side. All of these are done on DE1 So C FPGA platform. A PC decoder based on FFMPEG librarys is implemented to verify the correctness of encoding system and test coding performance. Experiment results on DE1 So C FPGA platform show that the system works at 720P@20FPS, and the quality of reconstructed frames is good.This paper accumulates experience for hardware/software co-design and implementation of video coding systems. The impletemented system plays a role on later research and has meanings in practical use.