Research And Hardware Implementation Of Deringing Algorithm In Video Coding

Vision is the most important way for people to get information outsides, that's why video technology has become a very important branch in multimedia. Since the information in video is huge, only by compressing original pictures using video coding can them be effectively stored and transferred.In order to improve compression ratio, the combination of lossy and lossless coding method is used in video coding systems. However, lossy coding will decrease the quality of images when the compression ratio is relatively high, meanwhile cause artifacts such as ringing effect. With the rising demand on high video quality, how to remove these artifacts has become a very important research branch. Post filtering is a main method to improve the quality of images and has wide application due to its easy implementation and low cost.In this thesis, we focus on the research and hardware implementation of deringing algorithm in post filtering of video coding. First, human visual system and its characteristics are introduced together with the main artifacts in video coding and the subjective and objective standards to measure those artifacts. Then we introduce the principle of deringing filter, current algorithms and their developing direction.With the consideration of human visual system and hardware implementation, some improvements are made to current deranging algorithm in this paper. In the proposed algorithm, firstly according to characteristics of human visual system, the boundaries in the image are detected to distinguish which area need to be filtered. Then according to the detecting result, adaptive window filter is used to deringing. While keeping the result of filtering, some more improvements are made at the same time. Some complex multiplies and divisions are simplified and the critical path is also reduced. Thus the hardware implementation costs less resource and has faster speed.At last, on ARM based SoC architecture, we realizes the proposed algorithm and the system in RTL level and finishes functional simulation using VCS and Matlab. After that, we synthesizes the RTL code using TSMC0.18 technical library whose result shows that the algorithm and hardware architecture is well designed and can meet the requirement of real-time processing.