Design And Optimization Of High Efficiency Entropy Coding Algorithm And Hardware Structure Based On AVS2

With the increasing demand for video resolution,the amount of information contained in each frame of video has risen sharply.With the increasing capacity of storage devices and the widening of the bandwidth of the transmission equipment,the pressure of video can be alleviated to a certain extent,but the development of storage and transmission technologies are still unable to match the growing video data.Video encoding technologies which compresses the original video signal,fundamentally solve the storage and transmission pressure of high-definition and ultra-high-definition video.In recent years,China has vigorously developed a video encoding standard with independent intellectual property rights.AVS2,as a new generation of video encoding standard in China,has more than doubled the compression performance of previous generation video encoding standard AVS,and can effectively compress high-definition and ultra-high definition video.However,with the improvement of compression performance,it also brings about an increase in computational complexity,which reduces the coding efficiency and makes it difficult to meet real-time requirements.With the improvement of hardware processing capability,VLSI has become one of the first choice of efficient coding platform.This thesis aims to improve the coding efficiency and reduce the computational complexity.From the perspective of entropy coding,the algorithm and hardware structure of AVS2 encoder are designed and optimized.The main contents of this thesis include:(1)From the perspective of a fast algorithm:a fast rate estimation algorithm is designed based on the encoding characteristics of entropy coding for rate generation process in rate-distortion optimization.Fit the corresponding model for the encoding of different syntax elements.The test results of encoding time,output bit rate,and peak signal-to-noise ratio PSNR are performed.The results show that the average encoding time can save 30.97%,and the average performance loss is 2.2%.(2)From the perspective of hardware structure:the hardware design framework of AVS2 advanced entropy encoder is proposed based on the characteristics of arithmetic coding.The design is parallel and efficient and mainly includes the following five technologies:the mechanism of three-level state control,unified management of reference data,parallelization of binarization algorithm,the technology of probability model access management,and the pipeline architecture of arithmetic coding efficient.This thesis uses verilog HDL hardware description language for each module and use modelsim to simulate.The simulation and synthesis results show that the proposed AVS2 advanced entropy encoder hardware structure can work at 300MHz frequency,meet the 150Mbit/s throughput rate,and can be used in the field of high-definition video real-time encoding of 1920x1080@60fps.