| Test cost comprises a substantial portion of producing an integrated circuit. As a result, structural modifications of the circuit via design for test (DFT) techniques are commonly used as an aid to reduce test cost to the lowest possible level. One important class of DFT is Built-In Self-Test (BIST). In BIST, test generation and response analysis logic is integrated into the original circuit and are transparent during normal operation. In this manner, in-circuit tests can be performed with minimal need of external test equipment, if any.;Test strategies based on pseudorandom test stimuli are attractive since the simplicity of the pattern generation logic facilitates on-chip test application. Unfortunately, until now, these methods have been more appropriate for testing combinational rather than sequential circuits. This is largely because, unlike combinational testing, detection of sequential faults can require specific orderings of circuit operations which are prohibitively difficult to produce using a pseudorandom source.;This thesis introduces a new DFT technique which permits at-speed on-chip sequential testing using parallel pseudorandom test patterns applied only to the primary inputs of the circuit under test. Test network design focuses on adjusting fault free circuit activity and aiding error propagation. This is done via the strategic insertion of a small number of low area test points. The resulting system is unique in that aside from a test mode flag, all I/O signals needed for test system operation are tapped from within the circuit itself. This feature virtually eliminates the control signal generation logic typically needed in other test point strategies. Also, as opposed to the conventional approach of restricting circuit alterations to the state elements, the proposed flexibility in choosing modification sites is beneficial when considering speed constrained designs.;Experiments demonstrate that high single stuck-at fault coverage is achieved for a number of benchmark circuits. |
