Automatic test generation techniques for sequential circuits

The research is targeted to develop effective techniques for (1) sequential circuit test generation for fault detection and diagnosis and (2) design for testability (DFT).; First, two DFT techniques based on clock partitioning and clock freezing are proposed to ease the test generation process for sequential circuits. In one DFT technique, a circuit is mapped into various pipeline configurations. In the other DFT technique, a circuit is reduced to a loopy pipe, i.e., a circuit without any global feedback loops; then clock waves are generated by the DFT logic to test the loopy pipe. Two opportunistic algorithms, which try to detect as many faults as possible using the least effort, are proposed for test generation. Experimental results show that the obtained fault coverage is significantly higher and test generation time is one order of magnitude shorter for many circuits. The DFT techniques do not introduce any delay penalty into the data path, have small area overhead, allow for at-speed application of tests, and have low power consumption.; Second, a low-power logic built-in self-test (BIST) technique, also based on clock partitioning and clock freezing, is proposed for transition fault testing of sequential circuits. Similarly, a circuit is configured into various loopy pipes, and pseudorandom vectors are applied to target transition faults. Experimental results show that the BIST technique has comparable transition fault coverage to the Scan BIST method for many cases and consumes much less power.; Third, a symbolic/genetic hybrid approach is proposed for sequential circuit test generation. A circuit is structurally divided into a controller and a datapath. Symbolic techniques are used to generate test sequences for the controller, and genetic algorithms (GAs) are used to generate sequences for the datapath. Experimental results demonstrate the efficiency of the hybrid approach.; Finally, a GA-based diagnostic test generation approach is proposed for sequential circuits. A simple GA, which interacts with an efficient diagnostic fault simulator, is proposed to target groups of undistinguished fault pairs iteratively. Efficient data structures are used and heuristics are proposed to seed the initial populations of the GA. Experimental results also demonstrate the efficiency of the proposed method.