Sequential Circuit Test Generation In A Number Of Key Technology Research

Testing operations significantly affect overall chip costs. The rapid increases in circuit size and resultant limited accessibility to internal signals have made automatic test-pattern generation one of the most difficult design problems in today's VLSI circuits. Fortunately, design for testability techniques have made ATPG somewhat easier for some circuit types. Nevertheless, equipping a circuit with complete scan path for such testing increases chip area and decreases circuit performance. Even worse, a complete scan design may be impossible. Thus, ATPG for sequential circuits is important in both industry and academia.Some key problems are discussed for sequential circuits testing generation in this paper, and present some new methods to improve the efficiency of sequential circuits testing generation.In the aspect of identifying feedback lines, we analyze the two different fanout stem types of sequential circuits, and present the ideas of the largest non-circle area for compressing the space of identifying and levelization from primary output to primary input to improve efficiency of identifying feedback lines.In the aspect of selecting sensitization paths in the logic iterative array, we present three rules of selecting sensitization paths for sequential circuits ATPG. The rule of expanding sensitization path can effectively reduce the number of backtracking in the process of selecting sensitization path.In the aspect of initialization of sequential circuits, we present the method based on the levelization of the store element's input line and its controllability to direct the initialized sequence of store element, meanwhile we combine the logic simulation to detect the initializability of store element, so as to shorten the vectors of initialization.In the aspect of untestable faults in the sequential circuits, we bring out...