Sequential circuit test generation

Automatic Test Pattern Generation (ATPG) is a process for generating tests for digital circuits. Due to the high computational complexity of sequential circuits, high fault coverage is not always guaranteed for different designs.; In this thesis, a fast and effective test generation system for synchronous sequential circuits described at the gate level is presented first. The test generation system, called MIX, combines several test generation approaches to derive test sequences exhibiting very high fault coverages at relatively low CPU times. Several new techniques are incorporated into MIX. Furthermore, a simplified form of test generation under the restricted multiple observation times test strategy is also employed. A parallel fault simulator is also developed to identify detected faults beyond those detected by conventional fault simulation. Moreover, MIX supports some industrial primitives besides the conventional Boolean primitives.; Next, a time-efficient procedure for identifying undetectable and redundant faults in a synchronous sequential circuit, without using a sequential circuit test pattern generator, is presented. The proposed procedure is based on the use of a limited length iterative logic array (ILA) model of the circuit, sequential static learning, and a subset of unreachable states in the fault-free circuit. The proposed procedure identifies a large numbers of undetectable and redundant faults in the sequential benchmark circuits using an ILA with length of 1 or 2. Based on the redundant identification procedure, another efficient procedure for removing subsets of sequentially redundant faults from synchronous sequential circuits with synchronizing sequences is presented. Instead of removing the redundant faults one at a time, properties of redundant faults are used to develop several methods to identify subsets of redundant faults that can be removed simultaneously from the circuit.; Finally, a test generation based partial scan design procedure is described. A new metric derived from the flip-flop activenesses in the sequential circuit and combinational test vectors is used to guide the flip-flop selection. In order to alleviate the computational complexity of invoking sequential test generation, the partial scan design is divided into three design phases which are applied from the least computationally intensive to the most computationally intensive.