Hot-carrier reliability simulation and verification

Hot carrier reliability is becoming an increasingly important problem as devices are scaled into the deep submicron regime. In the push for higher performance devices, hot carrier robustness has been compromised. At the same time, circuits are becoming more sensitive to hot carrier effects. Today, DC hot carrier lifetimes are sometimes less than 30 days, requiring the adoption of circuit-level hot carrier methodologies. This thesis explores circuit level hot carrier reliability issues and presents a number of simulation and verification solutions.; A statistical rule-based hot carrier simulator was developed that predicts the statistical distribution of path delay degradation caused by statistical variations in device hot carrier lifetime. The statistical simulator is useful for obtaining first order estimates of the impact of process variations on circuit level hot carrier reliability. In addition, experiments were performed to verify the accuracy of rule-based hot carrier simulation. A 64-bit adder was designed and fabricated in a 0.6μm CMOS technology and subjected to accelerated AC stressing. The measurement results showed good agreement with rule-based simulation results. A similar switch-level technique was also used to develop a fast electromigration simulator with the capability to simulate instantaneous fresh and degraded IR drops in power supply networks.; Voltage overshoot effects can reduce hot carrier lifetime by up to three orders of magnitude over typical AC stress. To better understand voltage overshoot, a full range of circuits were studied from an industrial 0.18μm CMOS technology, including static CMOS, pass transistor, and domino logic. Accurate simulation of voltage overshoot requires precise extraction of interconnect capacitance. A sensitive and simple technique, called Charge-Based Capacitance Measurement (CBCM), was developed which can measure interconnect capacitance down to the attofarad (10–18 F) range. The accuracy and validity of the technique was proven by measurement of several test structures in an industrial 0.5μm CMOS technology.; Reliability simulators such as BERT provide good accuracy, but are numerically inefficient and incapable of simulating large circuits. To address these limitations, a table-based methodology was proposed. The applicability of the table-based approach to timing simulation was demonstrated. Finally, a methodology was developed which can verify the reliability of a design without requiring designers to specify a set of worst case input vectors.