High field/high current reliability issues for deep sub-micron CMOS

This dissertation is a study of high field/high current reliability issues in deep sub-micron CMOS technologies namely bulk and SOI. Due to the ongoing shrinking of the transistors not only the reliability problems are increasing but also the interaction between reliability issues. For these reasons the results of this work are very timely especially with the emerging of new technologies like SOI and double gate MOSFETs.; A critical factor in the development of SOI wafers is the quality of the buried Si/SiO₂ interface. Careful wafer preparation is necessary to obtain reduced surface state density in order to suppress back channel leakage and improve hot carrier reliability and radiation hardness. A newly developed SOI MOSFET based “gated-diode” technique has been applied to study the buried SiO₂/SOI film interface. In order to evaluate the applicability of the technique and its sensitivity, increasing amounts of interface states were generated by two methods first by stressing it with hot carriers to the end of its lifetime and second by exposing the devices to increasing doses of 10-keV x-ray irradiation. Using “gated-diode” with device simulations and numerical analysis, we were capable of profiling the interface states and the trapped oxide charges along the channel length near the drain. We were also capable of determining the location of interface traps in the energy gap.; Electrostatic discharge (ESD) is another major reliability concern for devices in deep submicron regime. In this dissertation the high current characteristics encountered during electrostatic discharge (ESD) stress using NMOS/Lnpn protection devices in a 0.13 μm and 0.1 μm CMOS technology are investigated for different device parameters. From leakage current measurements following ESD stress, it is concluded that the shorter devices fail because of classical source/drain filamentation whereas longer devices with thin (22 Å) oxide gate fail because of oxide breakdown. This conclusion is consistent with and supported by numerical simulations of the electric field. It is also supported by the observed effect of hot carrier stress on It2. Hot carrier stress experiments additionally revealed that ESD stress can and often does affect subsequent hot carrier degradation of the device. The effect of the oxide degradation on the ESD robustness of the MOSFET devices is also studied showing that ESD design rules should take into consideration the degradation of the device for both hot carrier and oxide degradations to determine the size of the protection circuits.; Finally, this dissertation provides a study for the ESD protection capabilities of SOI vs. bulk MOSFET, and the protection circuits designed especially for SOI. A preliminary study for the high current characteristics of the double gate structure was also provided which can be the basis to design protection circuits for this new structure.