Modeling, simulation and design of EOS/ESD protection devices and circuits in silicon-on-insulator technology

Silicon On Insulator (SOI) technology is an ideal candidate for low-voltage electronics and has a number of advantages over bulk-Si technology in speed, processing costs, area, latchup, etc. However, devices used for providing protection against Electrical Overstress (EOS) and Electrostatic Discharges (ESD) are weaker in SOI technology. Electrical overstress and electrostatic discharges are major causes for integrated circuit (IC) field failures. Industry surveys indicate that nearly 50% of all IC field failures can be attributed to EOS/ESD events. Therefore, the aim of this thesis is to model the electrical and thermal characteristics of SOI protection devices and be able to simulate protection circuits under ESD stresses.; Because thermal failure is one of the most prevalent failure mechanisms during a Human Body Model (HBM) ESD stress, we first address the dynamics of heat flow in SOI devices. Power-to-failure versus time-to-failure profiles for SOI protection devices are generated through a consideration of Joule heating. Experimental results are presented to justify assumptions made in the investigation of heat flow in SOI devices. A lossy transmission line equivalent model has been used to model the heat diffusion problem. A design space for multifinger NMOS protection devices has been developed on the basis of self-heating constraints. The method of images has been used to transform the multifinger device to an equivalent single-finger device to simplify the heat-flow analysis.; During pulsed stressing of SOI MOSFETs for ESD characterization, the turn-on voltage of the parasitic bipolar transistor was observed to be a function of the stress pulse-width. This observation can be understood in terms of a capacitive charging model. The theory behind this time-dependent snapback is presented in this thesis along with the experimental results. Various novel protection structures and compact protection schemes have been suggested using the time dependence of BJT triggering voltage.; For the first time, a circuit level simulation tool for CMOS-on-SOI ESD protection networks is presented. The simulator, SOI-iETSIM, has built-in device models for completely coupled electrothermal simulation of SOI protection devices operating in the high current regime. The implementation of thermal models in a circuit level simulator for SOI circuits is discussed. Modeling the floating body effects in SOI MOSFETs and their effect on the device operation in the snapback mode is also discussed. The implementation of the parasitic BJT in the SOI MOSFET model is different from previously published models. Device simulation examples and an SOI-ESD protection circuit simulation example are also presented.