| The wireless market is currently experiencing a huge growth in terms of both the number of users and the range of services offered. With this growth, there is an acute demand for reducing the cost and size of the device and increasing the lifetime of its battery. In achieving this, a high level of performance must be maintained in order to meet the stringent requirements of the wireless system.; A major and critical component of a wireless transceiver is the frequency synthesizer. Its performance affects many of the requirements imposed on the transceiver, such as speed, sensitivity, and adjacent channel rejection. Being active for a large proportion of the time, it has a significant effect on the battery life. In addition, it is prone to interference with other components such as the power amplifier. The objective of this thesis is to enhance the performance of the wireless frequency synthesizer through architectural innovations. PLL architectures that attempt to improve the phase-noise while meeting the spurious requirements are presented.; A key improvement that this work tries to achieve is the ability to meet the stringent phase-noise requirements using monolithic integrated VCOs. Not only does this lead to a significant reduction in the cost and size of the radio, but also to much less interference and leakage problems. Furthermore, the use of an on-chip VCO eliminates the power needed to drive off-chip 50Ω impedances.; In this thesis, we present three different phase-locked loop architectures that attempt to reduce the VCO phase-noise and enhance the synthesizer performance. The first architecture is a nested-loop PLL that achieves very wide BW while maintaining the required frequency resolution and spur rejection. The wide-BW loop, including the loop filter, is integrated on a single chip in a 25GHz bipolar process. The PLL achieves a phase-noise of −100dBc/Hz at 10kHz offset from 1GHz and consumes 9.9mA from a 3.3V supply.; The second architecture is a frequency synthesizer based on a novel closed-loop voltage-to-frequency converter. A VCO is configured in a wide-bandwidth voltage-locked feedback loop that suppresses the VCO phase-noise. By configuring this architecture in a PLL, low phase-noise frequency synthesis is possible using integrated VCOs. The proposed architecture is designed in a 0.8μm BiCMOS technology and achieves up to 20dB reduction in the integrated VCO phase-noise.; Finally, we investigate the use of subsampling in frequency synthesis. A novel PLL architecture that employs subsampling in the feedback path is presented. The loop eliminates the prescaler and greatly reduces the division ratio. The architecture is particularly suitable for DDS-driven PLLs since it relaxes the requirements on the DDS thus further reducing the power consumption. The advantages of the architecture are highlighted and the design considerations discussed. System-level simulations are also presented. |
