| Wireless communication systems represent one of the largest consumer electronic markets, and the digital components in these systems provide the most challenge for digital designers. The wireless digital designs need to not only provide high performance, but also low power usage and small form-factor. Recent wireless applications add a new metric, flexibility, into the implementation requirements. This digital design paradigm calls for implementations that are heterogeneous (which includes ASIC, programmable processor, and reconfigurable components) to meet the requirement of providing performance, energy efficiency, and flexibility. A design methodology that takes all the design metrics and architecture styles into account is needed. This thesis proposes an energy-conscious methodology that can be used to synthesize or compile to such heterogeneous digital-signal processors. The goal of this research is to develop a design environment that takes the digital-signal processing algorithms specified in a high-level language, and provides guidance to perform hardware-software-reconfigware partitioning and synthesis under real-time performance constraints and optimization objectives (such as low-energy consumption). This methodology is based on collecting quantitative power-delay-area information about the algorithm and architecture, then combining the information to guide architecture mappings and partitioning. A step-by-step procedure is presented (computational bottleneck extraction, mappings from algorithm to architecture, hardware-software-reconfigware partitioning and optimizations specific to reconfigurable architectures). A set of tools to assist in performing tasks in each step is developed. At the end of the thesis, a design example that results in a low-power heterogeneous source-CODEC processor is presented. |
