| This research work proposes a new methodology to derive reconfigurable heterogeneous hierarchical routing architecture by exploiting the computation characteristics of the target application domain. High-throughput technologies have led to an exponential growth in the amount of data generated in the fields of geophysics, biosciences, signal processing, video compression and computational fluid dynamics over the past several years. This data explosion is forcing scientists to search for innovative computational designs to meet the growing demands. There is evidence that reconfigurable systems can deliver 10X to 100X or greater improvement in computational efficiency for many computationally intensive problems by tailoring hardware allocations to match the needs of applications. This significant speed advantage is due to the highly parallel nature of FPGA (Field Programmable Gate Array) hardware. Fortunately, many problems in those application domains are inherently parallel, and benefit from concurrent computing models. However, FPGAs suffer from the drawbacks of being application agnostic and hence incur penalties of loss of clock cycles in redundant reconfigurations, generic routing and poor memory architectures which impact speed, power and silicon area. All these factors have led us into exploring the application specific reconfigurable architecture design space. Research methodology involves: (a) control flow graph generation through LANCE compiler, (b) mapping of pure data dependent computations within the control flow structures into LUTs, (c) packing LUT based netlists into processing elements, (d) forming hierarchy of clusters, (e) deriving switching and wiring requirements and finalizing the routing architecture. Applications are then mapped on the processing elements based on the architecture constraints; placed and routed using existing placement and routing algorithms. This methodology proposes to provide optimum interconnection pathways, by allocating just enough switching and wiring resources by profiling the computational characteristics of the application. Only necessary and sufficient FPGA circuitry are synthesized for each task and every gate processes useful information in each clock cycle, therefore increased circuit-packing density can be achieved. Tools implemented as part of the methodology will permit seamless algorithm design at a high level of abstraction and execution at a high level of efficiency in hardware, synthesizing layers of parallel execution structures all the way to the gate level. |
