| Many applications that are run on embedded sensors, especially vision applications, require the computationally intensive processing of sensor data in real-time. Constrained embedded processors are usually incapable of providing the required performance, which forces these applications onto hardware. However, typical applications perform different computations/algorithms, depending on the events occurring at runtime. Therefore, a dynamically adaptive implementation is called for. Reconfigurable hardware is singularly capable of providing the required real-time performance, while still allowing dynamic adaptability.; The objective of this thesis is to introduce reconfigurable computing as a powerful solution that provides both flexibility and realtime performance for embedded applications. The thesis provides an overview of the GALORE (Globally Ad-hoc Locally Regular Embedded systems) project, which investigates the challenges involved in performing applications using a network of heterogeneous and reconfigurable computation resources. A dynamically-reconfigurable collaborative object tracking system is presented, which is built with a network of cameras equipped with embedded processors and FPGAs. This system has not only served as a testbed for experimenting with proposed techniques, but has also motivated new problems, which have far reaching applications, outside of this specific system.; Two major problems, namely, computation and resource management and reconfiguration sequence management, are highlighted. Computation and resource management is the problem of selecting the proper implementation for each computation, and selecting the proper resource in a network of heterogeneous resources for executing each computation, while meeting real-time performance constraints and maximizing some reasonable gain function. An example of gain function would be tracking accuracy. A novel and efficient combinatorial technique is presented that solves the problem for several widely-used cost functions. This methodology is applicable to many other application domains, ranging from sensor networks to electronic design automation to project management.; Reconfiguration sequence management deals with the order in which different hardware designs are being instantiated on the reconfigurable hardware. The order can affect the runtime reconfiguration delay, which dominates the total application runtime for many classes of applications. A theoretically optimal technique has been developed and presented in this thesis, which is applicable to single/multi FPGA systems, as well as partially reconfigurable hardware devices. |
