| This thesis consists of two major objectives in the digital circuit area. The first objective is the VLSI implementation of a high speed 2/3 Viterbi Decoder (ISO/IEC 16500) for a MMDS receiver using an automatic synthesis design flow. The design was implemented using TSMC CMOSP35 technologies using Verilog HDL, Cadence, and Synopsys. The results from different operation implementations are compared in order to improve speed. Union Bounds and computer simulations are also used to investigate the performance of the 2/3 convolutional coding. As well, an effective hardware implementation is developed to prevent overflow. The decoder, using a pipelined structure, achieves a maximum frequency of 120 MHz which corresponds to a baud rate of 240 MHz.; The second objective of this thesis is to model and analyze noise effects in self-timed and synchronous digital circuits, with an emphasis on low voltage operation and high speed issues. Simulations show that noise performance of a self-timed system can be superior to that of a functionally-equivalent synchronous one, especially at higher operating speeds. Test results of a digital circuit in CMOSP35 also confirm these results. For I/O drivers, simulations show that the I/O pads of a self-timed system can have better noise performance than that of a synchronous system. |
