For Digital Multimedia Broadcasting System Forward Error Correction Code Decoder Principles And Vlsi Implementation

Ever since the foundation of "Information and coding theory" by Claud Shannon in 1948, the channel coding technology has become an indispensable and special branch in modern communications after 60 years of development. There are applications of forward error correction technology everywhere, from cable modems in the early years to multimedia broadcasting systems and mass storage devices nowadays. As Shannon's theory only points out the theoretical limit of reliable communications, the FEC researchers have been mainly focusing on finding capacity-approaching codes and decoders which are fit for hardware implementation.In these days, the digital TV has been very popular over the whole world, it is said to be the second revolution in TV sets (the first revolution in TV sets is the transformation from black and white TV sets to color TV sets). The US is going to force the implementation of digital TV standard from 2006, and China will shut down the analog TV service in 2015．As one of the core technology in digital multimedia broadcasting systems, the demodulation chip has been the hot research topic in many research institutions; and the FEC modules have inevitably been one of the important parts in digital multimedia broadcasting systems.After research and analysis of many different digital video broadcasting standards in existence, we have focused on two representative digital video broadcasting standard: the DVB-C standard from Europe and the DMB-T standard from China. The DVB-C standard uses the classic Reed-Solomon code as its FEC solution, and the DMB-T standard uses the LDPC-BCH concatenated codes as its FEC. In this paper, we propose VLSI architectures for a Reed-Solomon decoder in the DVB-C receiver and for an LDPC decoder in the DMB-T standard.The following original and creative ideas have been proposed during searching for VLSI solutions of the above FEC decoders: (1) in decoder design for the shortened (204,188) Reed-Solomon codes in DVB-C standard, we use modified Euclidean algorithm to gain regular hardware architecture, and take advantage of the multi-rate clocks in the DVB-C system to optimize the decoder pipeline by making different modules in the decoder working under clocks with different rates; (2) an LDPC code encode algorithm based on the LU factorization with pivoting is proposed as well as the encoder VLSI architecture, the proposed encoder can be applied for most randomly designed LDPC codes and it has a linear complexity with the code lengths; (3) The low-complexity LDPC decoding using the partial-min algorithms is proposed, which can effectively lower the check-node complexities and reduce the on-chip memory sizes; (4) an LDPC decoder IP for the DMB-T receiver is specially designed with technologies like compact pipeline architectures, overlapped message passing, half-broadcasting belief propagation, etc.Both algorithmic solution and ASIC, FPGA solutions are provided for the RS decoder in DVB-C demodulator and the LDPC decoder in DMB-T demodulator. The algorithmic solution includes regular decoding algorithms and optimizations of the algorithms proposed by the author; fixed-point and float-point performance evaluations and complexity analysis is provided for every algorithm. The VLSI solution includes detailed hardware framework architecture, detailed implementations of different sub-modules, data flow analysis and pipeline optimizations. The comparisons with the other implementations in literatures are also provided.At last, the FPGA and ASIC implementation results are provided for the RS decoder in DVB-C demodulator and the LDPC decoder in DMB-T demodulator. Field test and lab test results show that the algorithms and VLSI solutions proposed by the author have met the requirements of commercial applications.