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Design and optimization of global interconnect in high speed VLSI circuits

Posted on:2003-06-20Degree:Ph.DType:Thesis
University:University of MinnesotaCandidate:Su, HaihuaFull Text:PDF
GTID:2468390011986866Subject:Engineering
Abstract/Summary:
This thesis consists of three parts, corresponding to various aspects of global interconnect design issues.; For the design and optimization of power distribution networks, we propose a structured skeleton that is intermediate to the conventional method that uses full meshes which are hard to analyze efficiently, and tree-structured networks, which provide poor performance. As an example, we consider a power/ground (P/G) network structure modeled as an overlying mesh with underlying trees originating from the mesh, which eases the task of analysis with acceptable performance sacrifices. A fast and efficient event-driven P/G network simulator is proposed, which hierarchically simulates the P/G network with an adaptation of PRIMA to handle non-zero initial conditions.; For ASIC-like circuits, the addition of decoupling capacitances is arguably the most powerful degree of freedom that a designer has for power-grid noise abatement. We propose and demonstrate an algorithm for the automated placement and sizing of decaps and show that this allows power grid noise to be significantly reduced with little change in the total chip area.; Next, the idea of a hybrid mesh/tree structure is applied to the design of clock distribution networks. We hierarchically construct a hybrid mesh/tree clock network structure consisting of overlying zero-skew clock meshes, with underlying zero-skew clock trees originating from the mesh nodes. We propose a mesh construction procedure, which guarantees zero skew under the Elmore delay model, using a simple and efficient linear programming formulation.; Finally, a global wire design methodology that simultaneously considers the performance needs for both signal lines and power grids under congestion considerations is presented. An iterative procedure is employed in which the global routing is performed according to a congestion map that includes the resource utilization of the power grid, followed by a step in which the power grid is adjusted to relax the congestion in crowded regions. This adjustment is in the form of wire removal in noncritical regions, followed by a wire sizing step that overcomes the effects of wire removal. The overall routability is demonstrated to be significantly improved while the power grid noise is maintained within a specified constraint. (Abstract shortened by UMI.)...
Keywords/Search Tags:Global, Power grid
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