| As modern IC design gradually enters ultra-deep sub-micron (UDSM) regime, higher device densities and faster switching frequency cause on-die power distribution network to burden higher voltage droop. Excessively high power grid noise may not only lead to functional failures, but also greatly shorten the die's lifetime because of unevenly distributed currents. Therefore, it's of high importance to analyze on-die power grid noise and optimize power grid network. This thesis will focus on the issues related to on-die power integrity.Modeling, analyzing and optimizing are very challenging for on-die power grid network due to its large scale and complexity. A serie of novel modeling, analyzing and optimizing algorithms have been proposed in this thesis based on studying of existing algorithms, which involves the modeling algorithm of on-die power grid interconnect, fast analysis algorithm for on-die power grid, power pads and on-die decap placing and optimizing algorithms, constructing method of simplified on-die power grid model and EDA software design for on-die power integrity analysis. The main contributions of this thesis can be summarized as the followings:1) The effect of power grid network's parasitics and transistor-level model on power grid noise is analyzed. A novel chip partial effective inductance extracting method based on limited return path and table-loopup has been proposed, and the superior performace is verified from efficiency and accuracy views.2) To overcome the inefficiency of random walk when solving for entire network, we propose an improved random walk method for power grid analysis. The improved algorithm is ten times speedup with negligible error for certain designs. Using the improved random walk method as preconditioning algorithm, a novel preconditioning Gause-Seidel method is proposed which shows 5 times speedup compared with ICCG method and also has the advantages of being easy to be parallized and high parallel efficiency.3) We propose an algorithm for power supply pads assignment based on random walk algorithm. This algorithm can efficiently decide nearly optimal locations or the number of power supply pads given the number of power supply pads or voltage droop margin.4) A simplyfing algorithm of on-die power grid model based on Norton's theorem is proposed. This algorithm firstly uses proposed fast Y parameter calculating algorithm to obtain Y parameter among targeted ports of power grid, and then uses vector fitting algorithm to synthesize the simplified circuit model accurately and efficiently, and lastly adopts random walk algorithm to efficiently extract current signature at target ports of power grid. Thus the whole simplified on-die power grid model is generated including passive part and active part. Experimetal result verifies the algorithm's precision and high efficiency. This model can be used for co-analysis and optimizing of chip-package-pcb power distribution network.5) A novel on-die decap optimizing algorithm considering the chip-package resonance is proposed. In this algorithm the simplified-like algorithm for on-die power grid model is firstly used to calculate device's switching mode which generates worst power grid noise, and then random walk algorithm is adopted to optimize the decap placing part by part, thus the accuracy and efficiency is guaranteed to apply this algorithm to full-chip level optimizing.6) How to design GUI based on-die power integrity analysis tools is studied and an on-die power integrity analysis tool named as "IC P/G Simulator" is designed, which is based on related algorithms proposed in this thesis and has most of the needed functions.
|
PDF Full Text Request