Modeling of power supply noise in large chips using the finite difference time domain method

The goal of the dissertation was to demonstrate the feasibility of simulating power supply noise at the system level. In particular, the thesis was targeted towards CMOS based systems containing large chips in multi-layered packages and boards. This dissertation used the Finite Difference Time Domain (FDTD) method to solve the circuit equations extracted from the physical dimensions of the interconnections in the power distribution network. The FDTD method had been extended to include non-linear circuits, and verified with SPICE. Using the FDTD method, the effect of excessive power supply noise on the output of non-linear circuits had been quantified. The cavity resonator model for multiple planes was implemented using the FDTD method. This was combined with the flip chip inductance, via inductance and solder ball inductance to capture the vertical and lateral parasitic inductance/capacitance in the package and board power distribution network. An important effect that is often neglected in the computation of power supply noise is the interaction between the chip-package and package-board. This interaction can cause additional resonances in the system. If these resonances have sufficient magnitude and are triggered during system operation, excessive noise can be generated in the system. The purpose of the co-simulation was to capture these resonances that are otherwise absent when each section of the system is analyzed.