| The functional performance of switched capacitor circuits is directly affected by variations in capacitor ratios. We have proposed a sigma-delta design technique to accurately measure these capacitor ratios. In this research work we develop an optimal procedure to minimize the number of capacitor ratios that need to be measured while still maintaining the desired fault coverage. We make use of the sensitivity of individual performance specifications to the specific capacitor ratios.; The basic test strategy is that during test mode the Circuit Under Test (CUT) is reconfigured to operate as an Analog-to-Digital Capacitor Ratio Converter (ADCRC), which digitally measures an optimally chosen set of capacitor ratios, and the measured data is used to determine if the given CUT meets the specifications.; The proposed technique has been validated with a number of examples including a first order lossy integrator, a second order low pass filter and sixth order high Q bandpass filter. As a more practical application, an 11-bit charge redistribution A/D converter with an ADCRC embedded, is fabricated in an 1.2μ CMOS process and tested. To illustrate the applicability of the proposed technique to testing static performance of the A/D converter we measure, derive, and analyze the non-linearity errors such as the integral non-linearity (INL) and differential non-linearity (DNL) errors during either normal and test mode, respectively, then compare them.; The procedure developed in this thesis can be easily applied to detect parametric faults in any switched capacitor circuit. |
