| To ensure the correct operation of synchronous digital circuits at high speeds of operation, it is of paramount importance to test them for delay faults. The path-delay fault model is the most comprehensive delay fault model that tries to ascertain the circuit under test is free of delay faults due to physical defects and random process variations. However, the very large numbers of paths in many combinational circuits, especially data path circuits (DPC), create great difficulties in applying existing delay test techniques. In this research, we use the regularity of DPCs to solve some of the most challenging problems in delay testing namely, test generation, fault simulation and design for testability for DPCs.; We demonstrate a non-enumerative test generation methodology for 1-dimensional iterative logic arrays (1-D ILAs) that uses the following components: gate-level circuit description and state table, module interconnection, test graph, and path expressions. We show the results that indicate the effectiveness of our approach. First, our approach is applicable to large ILA sizes, where existing methods fail. Second, our approach decreases drastically the storage required in automatic test equipment, thereby significantly decreasing the cost of testing.; We propose a non-enumerative approach to path-delay fault simulation of DPCs as well as other circuits with large numbers of paths. The non-enumerative approach uses path-graphs to store information pertinent to tested paths. It relies on the principle of inclusion and exclusionto obtain the fault coverage of a test set. In order to cope with the large number of intersection operations required, we have devised a novel encoding algorithm that significantly reduces the number of intersection operations. Finally, we describe the components of a design for testability approach that uses the test graph, connectivity graph and state table to identify hardware changes to the basic module in order to enhance the path-delay testability of an ILA and reduce the delay penalty incurred on critical paths due to the hardware changes. |
