A gate-level timing model for SOI circuits

Partially depleted floating-body (PDFB) SOI technology offers the potential of increased speed and lower power dissipation over traditional bulk CMOS. A key problem, however, related to the use of traditional design flows for new SOI designs is that the threshold voltage of the PDFB SOI transistors and therefore the delay of logic gates built of these transistors varies according to the signal history. In this thesis, we have formulated a simulation model that allows one to track the changes in delay during a dynamic gate-level simulation of the PDFB SOI circuit, without the direct use or tracking of the body node voltages. This is essential in order to properly account for the shift of transistor body voltage in SOT devices. The model captures the "state" of a logic gate via two delay "state variables" for each timing arc which represent the rise and fall time delay of the timing arc.