Integrating timing diagram protocols with HLA simulations

Manufacturers and integrators of hardware components and Systems-on-Chip Intellectual Property need to model and simulate the hardware interfacing behaviors of the product before the physical integration into a hardware system. This thesis focuses on the simulation of hardware systems interfacing behaviors based on the system components' signaling scenarios in the modeling process. Timing diagrams are employed to specify the signaling scenarios since timing diagrams have a wide acceptance among hardware professionals in describing, visualizing and analyzing signaling behavior and timing relations. The High Level Architecture (HLA) is used as a simulation platform since the HLA has gained rapid popularity for supporting simulation interoperability and reusability. The thesis proposes a simulator architecture and design, which follows the object-oriented paradigm and satisfies simulation interoperability goals. The proposed architecture reuses component simulations, which interact at levels of abstraction above the details of signaling, and introduces new modules that encapsulate and enable signaling behaviors.