| Efficient hardware/software codesign framework will greatly facilitate not only the design but also the verification early in the embedded system deign cycle. With these electric design automation (EDA) tools, the hardware can be concisely modeled at a higher abstraction level better than with the more traditional hardware description languages. SystemC is such a hardware/software codesign language, which allows hardware models to be written in C++. Consequently, it is naturally needed to consider a hardware implementation for the verified SystemC models.;To solve this bottleneck problem, two design flow methodologies, namely direct synthesis method and indirect synthesis method, are proposed in the literatures. Since the indirect synthesis method applies the traditional hardware design language (HDL) synthesis technology as part of its design flow, it is considered as framework solution. As result, the compiler tool, which translates SystemC to VHDL, is presented in the thesis. The details of equivalent constructs between these two languages are illustrated. Besides performing obvious translation of many SystemC elements, the compiler focuses on the automated translation of control structures and expressions. Finally, a series of digital application modules in SystemC were tested. Simulations of the translated VHDL models yielded the expected results. |
