Research Of VHDL Compiler's Design Techniques

With the development of VLSI (Very Large Scale Integration) ,More big challenge is faced for designers. It is necessary to design chip with HDL(Hardware Description Language) and HLS(High-level Synthesis) which also is called behavioral synthesis.The main task is translating the behavioral description of a digital system into the design of RTL(Register Transfer Level).The HLS skill can help designers begin from higher level and complete the whole design from top to down spanning some levels, it will effectively enhance the capability of digital circuit design and greatly shorten the design cycle.The research for tools of HLS is also be paid much attention to,The most famous tool of behavioral synthesis is BC.This paper is about design and reaearch of the VHDL compiling system based on the subset of IEEE 1076.The VHDL compiling system is the front-end of the VHDL high-level synthesis system,it accept VHDL source description and generate a interface format used by the latter synthesis or simulation systems.This system is developed under Windows's environment,and using Parser Generator 2.0 and C to accomplish the implement of lexical analyzer and grammar analyzer.The advantange of it is advancing the developing speed and convenient to maintenance and transplant of the system.In the paper,we pick up a subset of VHDL, absorb the basic and widely used grammar struct,wipe off the struct that almost not be used.this shorten the size of compiling system and improve the compiling efficiency.Based on the research ofVHDL lexical rules,we present the way of classifying VHDL lexical elements.Meanwhile,we take such techniques as reducing the scale of lexical expression and pre-processing.In the end, the scale of lexical analyzer was greatly decreased and the compiling speed was improved .In the implement of grammar analyzer,we finish the translating of the grammar struct.especially,we have a deep study on the problem of expression translating and the struct which has different meanings.we prsent the way to resolve these problems. We use hash technology to manage the symbol list, and manage the information of levels by establishing a dynamic stack. At last, we extract the behavioral information by searching the statement-list and translate it into CDFG as the last output of compiling system.besides these,Our system also have good error management.Besides this compiling system ,in order to have readers have a clear knowledge to the role of compiling system in high-level synthesis,we also make a simple introduce the full flow of high-level synthesis in chapter One.Our compiling system have passed many examples.lt have the perfect support for the common logic arithmetic, condition branch and repeating statement, processment statement, and other basic struct.because of the specialness,Our system have advantages such as small size, rapid speed of compiling and so on.The CDFG generated have completed information and clear structgiving perfect support for the latter development of synthesis and simulation system.