Key Problems On Transforming VHDL Into MSVL Programs

Very-High-Speed Integrated Circuit Hardware Description Language(VHDL)is a high-level computer language for circuit design.VHDL is widely used in the field of electronic engineering for its design flexibility and powerful hardware description capability.However,with the ever-changing demands of digital circuit design and the increase of hardware complexity of large-scale digital circuit systems,the correctness and efficiency of hardware system design becomes more and more important.The existing tools analyze and estimate hardware system models to some degree by using some simulation tools of software,hardware or a combination of the two methods.But commonly used simulation tools is complex and expensive,with a large limitation,Therefore,how to validate the correctness of hardware system design through effective means becomes a difficult problem in hardware design.In the form of formal verification,temporal logic,as a powerful theoretical tool,is becoming more and more popular in the field of hardware and software system design.A series of tools developed on the basis of temporal logic can simulate and verify the hardware system model,so as to detect errors in the system model and improve them.Modeling,Simulation and Verification Language(MSVL)is a framed temporal logic programming language.In this paper,VHDL language is transformed into the same semantic MSVL language,and the transformed MSVL language is simulated,modeled and verified to detect whether the hardware system model described in VHDL language satisfies the expected properties.The main contents of this paper are as follows:1.In order to realize the transformation of two languages,this paper studies the features of the two languages,designs and implements the lexer and parser for their lexical and syntax rules.2.The system has designed and implemented the transformation rules from VHDL to MSVL.The system first uses lexical analysis and syntax analysis of the VHDL code,which is waited to be verified,to obtain its corresponding syntax tree and then uses the conversion rules to get the equivalent MSVL program.Due to the large differences in the internal mechanisms of the two languages,the validity of the conversion rule design is critical.This paper studies several key issues in VHDL to MSVL transformation: variable management processing,function name renaming problem processing,nested call handling between components,library package file parsing,and interface mapping problems processing etc.And the concrete solution is given to each key question.3.In order to verify the correctness of the transformation work,this paper implements a real-time simulation system based on the MSVL compiler.The system realizes the real-time simulation of the converted MSVL program,and analyzes the results of real-time simulation and further validates it.Multiple test cases show that the key problems in the VHDL to MSVL transformation system have been solved,and transformation system gets a better performance,with higher feasibility and reliability.