Design Of Digital Circuits, Fault-tolerant Design Automation-vhdl Compiler

It is a major concern for designer to consider fault tolerant in electronic devices along with the more and more high reliability requirements of system of digital circuit. Fault tolerance has been taken into account for many years during design process of these applications, but it has not obtained any profit of latest advances in automatic CAD tools that optimize the design process. Therefore, in order to enhance productivity, reduce development time and accelerate the development of fault tolerance circuits, an automatic CAD tool is needed. Furthermore, now most designers work mainly at the RT level on the process of designing the digital circuit, on the other word, the digital circuit is designed on VHDL description. In this paper we propose a tool for the automatic insertion of fault-tolerant structures in a VHDL synthesizable description of the design. With this tool, fault-tolerant design can be automatically produced in a VHDL description according user Specifications, which could be simulated and synthesized with commercial tools.In order to realize the tool for the automatic insertion of fault-tolerant structures, firstly, we need to resolve the key problem that is the development of VHDL compiler. The VHDL compiling system is the front-end of the VHDL high-level synthesis system. It accepts VHDL source description and generates an intermediate format for fault-tolerant-DAG, which is used by the latter process of inserting fault-tolerant structures. This system is developed under Windows's environment, and using some of compiler tools and C to accomplish the implement of VHDL lexical analyzer and grammar analyzer. The advantage of which is advancing the developing speed and convenient to maintenance and transplant of the system.In the implement of lexical analyzer, we present the way of classifying VHDL lexical elements. In the implement of grammar analyzer, we finish the translating of the grammar structure. Especially, we have a deep study on the problem of the structure, which has different meanings and conflict, and we present the way to resolve these problems. We use hash technology to manage the symbol list, and manage the information of levels by establishing a dynamic stack. At last, we build the intermediate format for VHDL descriptions by means of class. The intermediate format has completed information and clear structure, which gives perfect support for the latter process of inserting the fault-tolerant technology. In this paper we mainly realized the application of the passivity hardware tolerant technology.