High-speed digital ICs in transferred-substrate HBT technology | Posted on:2002-09-15 | Degree:Ph.D | Type:Thesis | University:University of California, Santa Barbara | Candidate:Mathew, Thomas | Full Text:PDF | GTID:2468390011496376 | Subject:Engineering | Abstract/Summary: | | One of the key electronic component needed for next generation naval radars is the direct digital frequency synthesis (DDFS) block, that is used for signal generation. A key building block in a DDFS system is the phase accumulator (adder-accumulator). The maximum clock rate (fck) of the various building blocks in a DDFS system determines its frequency resolution and tuning range. The frequency tuning range of the DDFS system is from DC to ∼ (fck/3) and the frequency resolution is given by Δf = fck/2N, where N is the bit length of the phase-accumulator word.; This work presents the design techniques used to improve the clock rate of a 2-bit adder-accumulator circuit, which is used as the building block in an 8-bit pipelined adder accumulator. The first generation design used a wired OR/AND approach in the carry logic (AND-OR) circuit to increase the clock rate. The carry and sum logic circuit of the 2-bit adder was fabricated and tested. Measurements indicated a maximum clock rate of 8 GHz for the carry logic circuit and 14 GHz for the sum logic circuit. The second generation design used a new single 3-level series-gated logic gate that performed the AND-OR operation needed to realize the carry logic of a full adder. This carry logic circuit was then merged with the latches to realize a merged AND-OR Latch circuit. Simulations indicated that this 4-level series-gated structure was 1.8:1 faster when compared to the wired-OR/AND approach. The carry and sum logic of the second-generation 2-bit adder designs were fabricated and tested. Measurements indicated a maximum clock rate of 19 GHz for the carry logic circuit and 24 GHz for the sum logic circuit. A 75 GHz ECL static frequency divider was also fabricated as part of this work.; Attempts to extend a technology, which demonstrated circuits having tens of transistors, to realize circuits having hundreds of transistors, brings forth a new set of failure mechanisms. This work also presents the test structures designed to identify the various failure mechanisms and the statistical data collected from these structures. | Keywords/Search Tags: | DDFS, Rate, Logic circuit, Carry logic, Frequency, Generation | | Related items |
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