| Rapid advances in VLSI technology have enabled us to reduce the minimum feature sizes of transistors to sub-quarter microns and the switching times of MOS transistors to tens of picoseconds or even less. Unfortunately, this comes at a cost. Digital circuits have become subject to the same type of problem that analog integrated circuits have been affected by since their inception. That problem is noise. Although device noise sources (i.e., shot noise, flicker noise, thermal noise) are still not an issue in the digital circuits performance, external noise sources (i.e., crosstalk, power/ground (P/G) bounce) significantly degrade the performance and the reliability of digital integrated circuits.; The research presented in this dissertation focuses on noise analysis and optimization in high-frequency mixed-signal VLSI circuits.; As a first step toward understanding the noise effects, we explore circuit properties that help us derive closed-form expressions for the capacitive crosstalk noise of RC interconnects as well as the power/ground noise due to the switchings of off-chip drivers.; We study the effect of the (P/G) noise on the timing jitter of the phase-locked loop (PLL) clock generators. Stochastic models of the P/G noise in VLSI circuits for different values of on-chip decoupling capacitances are presented. The PLL timing jitter is predicted in terms of the statistical properties of the P/G noise.; Finally, in order to capture all the effects of on-chip interconnect, we provide model-order reduction techniques that use the balanced truncation method and extend this technique to a new spectrally-weighted balanced truncation that reshapes the frequency spectrum and accounts for process variations in order to obtain a new variational spectrally-weighted balanced truncation method.; The new methods and formulations presented in this thesis represent efficient and accurate techniques for the noise analysis and optimization in the mixed-signal VLSI circuits. |
