| With continuous scaling of VLSI digital circuit technologies, coupling capacitance between interconnect lines is comparable to or even larger than line-to-reference capacitance, and some of the signal lines need more accurate transmission line modeling, requiring the introduction of self and mutual inductances. Consequently, interconnect parasitic elements have become dominant over gate parasitics. These trends, and the increasing usage of dynamic circuits for speed and area requirements, are making signal integrity, one of the most critical metrics of performance. Noise can have adverse effects on functional correctness, power, timing, and reliability of CMOS digital circuits.; This work presents an analysis of deep submicron digital integrated circuits in the presence of self and mutual inductances, and illustrates that large error occurs in estimating signal behavior if inductances are neglected. A set of simple closed form expressions are presented to estimate signal behavior, and to intuitively understand some of the characteristics of integrated circuits in the presence of inductances. However, introduction of inductances makes circuit analysis significantly more complex as compared to circuits without inductances. This work presents an innovative technique for realizable reduction of distributed RLC interconnects circuits including electric (capacitive) and electromagnetic (inductive) coupling. Reduction of extracted netlists is an important step in the performance analysis of deep submicron circuits, since the large amount of data typically generated by extraction tools significantly affect run time and memory issues.; This work also presents closed form analytical solutions for noise as well as noise tolerance metrics for dynamic circuits to analyze the effects of increasing coupling. The analysis of noise in dynamic circuits indicates that noise in dynamic circuits can be made scalable to some degree. Signal deviation caused by noise can lead to functional failure in digital integrated circuits. It has been shown that both static and dynamic digital circuits can suffer logic failure due to noise depending on the switching condition and circuit topology. It is illustrated that increasing frequency may lead to higher probability of noise-driven logic failure due to the possibility of reduced voltage swing at higher frequencies.; Continuous scaling of technologies towards the nanometer range will severely enhance noise and other implications, such as, leakage current levels, contributing to new power consumption sources. These trends are challenging traditional ways of noise avoidance and timing management. Therefore, the presented work must be extended to attempt developing new techniques for better performance in terms of noise immunity, reliability, energy efficiency, speed, and area requirements. |
