FPGA architecture and performance measurement for fast area efficient Parallel-Prefix modulo 2('n)-1 adders

The Modulo adder is an instrumental arithmetic component in implementing online residue-based computations for many digital signal processing applications. It is also a basic component in realizing modular multipliers and residue to binary converters. Thus, the design of a high speed and reduced-area modular adder is an important issue. This thesis intends to implement fast area efficient Parallel-Prefix modulo 2n-1 adder using the Han-Carlson prefix structure and to compare it with the modified Kogge-Stone (KS) Parallel-Prefix modulo 2n-1 adder. The modulo adders would be simulated using VHDL (Very High Speed Integrated Circuits Hardware Description Language) followed by an implementation on a FLEX10K FPGA chip using MaxPlus II software.